# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display color processor

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display color processor, namely COLOR, provides hue, luma and
  saturation adjustments to get better picture quality and to have one panel
  resemble the other in their output characteristics.
  COLOR device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt2701-disp-color
          - mediatek,mt8167-disp-color
          - mediatek,mt8173-disp-color
          - mediatek,mt8195-mdp3-color
      - items:
          - enum:
              - mediatek,mt8188-mdp3-color
          - const: mediatek,mt8195-mdp3-color
      - items:
          - enum:
              - mediatek,mt7623-disp-color
              - mediatek,mt2712-disp-color
          - const: mediatek,mt2701-disp-color
      - items:
          - enum:
              - mediatek,mt6795-disp-color
              - mediatek,mt8183-disp-color
              - mediatek,mt8186-disp-color
              - mediatek,mt8188-disp-color
              - mediatek,mt8192-disp-color
              - mediatek,mt8195-disp-color
              - mediatek,mt8365-disp-color
          - const: mediatek,mt8173-disp-color
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: COLOR Clock

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description:
      Input and output ports can have multiple endpoints, each of those
      connects to either the primary, secondary, etc, display pipeline.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: COLOR input port

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          COLOR output to the input of the next desired component in the
          display pipeline, for example one of the available CCORR or AAL
          blocks.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        color0: color@14013000 {
            compatible = "mediatek,mt8173-disp-color";
            reg = <0 0x14013000 0 0x1000>;
            interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_COLOR0>;
            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
        };
    };
