Index of /orangepi-build/kernel/orange-pi-6.1-rk35xx/drivers/misc/habanalabs/include/gaudi2/asic_reg/
../
arc_farm_arc0_acp_eng_regs.h 04-Dec-2025 19:36 16170
arc_farm_arc0_aux_masks.h 04-Dec-2025 19:36 35435
arc_farm_arc0_aux_regs.h 04-Dec-2025 19:36 17015
arc_farm_arc0_dup_eng_axuser_regs.h 04-Dec-2025 19:36 1747
arc_farm_arc0_dup_eng_regs.h 04-Dec-2025 19:36 17743
arc_farm_kdma_ctx_axuser_masks.h 04-Dec-2025 19:36 5731
arc_farm_kdma_ctx_axuser_regs.h 04-Dec-2025 19:36 1655
arc_farm_kdma_ctx_masks.h 04-Dec-2025 19:36 8892
arc_farm_kdma_ctx_regs.h 04-Dec-2025 19:36 2380
arc_farm_kdma_kdma_cgm_regs.h 04-Dec-2025 19:36 709
arc_farm_kdma_masks.h 04-Dec-2025 19:36 16583
arc_farm_kdma_regs.h 04-Dec-2025 19:36 3883
cpu_if_regs.h 04-Dec-2025 19:36 18149
dcore0_dec0_cmd_masks.h 04-Dec-2025 19:36 9763
dcore0_dec0_cmd_regs.h 04-Dec-2025 19:36 1920
dcore0_edma0_core_ctx_axuser_regs.h 04-Dec-2025 19:36 1747
dcore0_edma0_core_ctx_regs.h 04-Dec-2025 19:36 2540
dcore0_edma0_core_masks.h 04-Dec-2025 19:36 17899
dcore0_edma0_core_regs.h 04-Dec-2025 19:36 4167
dcore0_edma0_qm_arc_aux_regs.h 04-Dec-2025 19:36 18743
dcore0_edma0_qm_axuser_nonsecured_regs.h 04-Dec-2025 19:36 1862
dcore0_edma0_qm_cgm_regs.h 04-Dec-2025 19:36 688
dcore0_edma0_qm_masks.h 04-Dec-2025 19:36 51930
dcore0_edma0_qm_regs.h 04-Dec-2025 19:36 28932
dcore0_edma1_core_ctx_axuser_regs.h 04-Dec-2025 19:36 1747
dcore0_edma1_qm_axuser_nonsecured_regs.h 04-Dec-2025 19:36 1862
dcore0_hmmu0_mmu_masks.h 04-Dec-2025 19:36 13355
dcore0_hmmu0_mmu_regs.h 04-Dec-2025 19:36 6841
dcore0_hmmu0_stlb_masks.h 04-Dec-2025 19:36 15996
dcore0_hmmu0_stlb_regs.h 04-Dec-2025 19:36 4011
dcore0_mme_acc_regs.h 04-Dec-2025 19:36 1755
dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h 04-Dec-2025 19:36 1040
dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h 04-Dec-2025 19:36 1031
dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h 04-Dec-2025 19:36 1040
dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h 04-Dec-2025 19:36 1031
dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h 04-Dec-2025 19:36 1022
dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h 04-Dec-2025 19:36 1013
dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h 04-Dec-2025 19:36 1022
dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h 04-Dec-2025 19:36 1013
dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h 04-Dec-2025 19:36 1022
dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h 04-Dec-2025 19:36 1013
dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h 04-Dec-2025 19:36 1022
dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h 04-Dec-2025 19:36 1013
dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h 04-Dec-2025 19:36 1022
dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h 04-Dec-2025 19:36 1013
dcore0_mme_ctrl_lo_arch_base_addr_regs.h 04-Dec-2025 19:36 1130
dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h 04-Dec-2025 19:36 2406
dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h 04-Dec-2025 19:36 1098
dcore0_mme_ctrl_lo_arch_tensor_a_regs.h 04-Dec-2025 19:36 2125
dcore0_mme_ctrl_lo_arch_tensor_b_regs.h 04-Dec-2025 19:36 2125
dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h 04-Dec-2025 19:36 2203
dcore0_mme_ctrl_lo_masks.h 04-Dec-2025 19:36 22056
dcore0_mme_ctrl_lo_mme_axuser_regs.h 04-Dec-2025 19:36 1770
dcore0_mme_ctrl_lo_regs.h 04-Dec-2025 19:36 4447
dcore0_mme_qm_arc_acp_eng_regs.h 04-Dec-2025 19:36 17274
dcore0_mme_qm_arc_aux_regs.h 04-Dec-2025 19:36 18167
dcore0_mme_qm_arc_dup_eng_axuser_regs.h 04-Dec-2025 19:36 1839
dcore0_mme_qm_arc_dup_eng_regs.h 04-Dec-2025 19:36 18863
dcore0_mme_qm_axuser_nonsecured_regs.h 04-Dec-2025 19:36 1816
dcore0_mme_qm_axuser_secured_regs.h 04-Dec-2025 19:36 1747
dcore0_mme_qm_cgm_regs.h 04-Dec-2025 19:36 674
dcore0_mme_qm_regs.h 04-Dec-2025 19:36 27890
dcore0_mme_sbte0_masks.h 04-Dec-2025 19:36 3486
dcore0_mme_sbte0_mstr_if_axuser_regs.h 04-Dec-2025 19:36 1816
dcore0_mme_wb0_mstr_if_axuser_regs.h 04-Dec-2025 19:36 1770
dcore0_rtr0_ctrl_regs.h 04-Dec-2025 19:36 8091
dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h 04-Dec-2025 19:36 7682
dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h 04-Dec-2025 19:36 6683
dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h 04-Dec-2025 19:36 7682
dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h 04-Dec-2025 19:36 6683
dcore0_sync_mngr_glbl_masks.h 04-Dec-2025 19:36 5332
dcore0_sync_mngr_glbl_regs.h 04-Dec-2025 19:36 34068
dcore0_sync_mngr_mstr_if_axuser_masks.h 04-Dec-2025 19:36 6410
dcore0_sync_mngr_mstr_if_axuser_regs.h 04-Dec-2025 19:36 1816
dcore0_sync_mngr_objs_masks.h 04-Dec-2025 19:36 3557
dcore0_sync_mngr_objs_regs.h 04-Dec-2025 19:36 1256314
dcore0_tpc0_cfg_axuser_regs.h 04-Dec-2025 19:36 1609
dcore0_tpc0_cfg_kernel_regs.h 04-Dec-2025 19:36 3500
dcore0_tpc0_cfg_kernel_tensor_0_regs.h 04-Dec-2025 19:36 1966
dcore0_tpc0_cfg_masks.h 04-Dec-2025 19:36 22268
dcore0_tpc0_cfg_qm_regs.h 04-Dec-2025 19:36 3272
dcore0_tpc0_cfg_qm_sync_object_regs.h 04-Dec-2025 19:36 716
dcore0_tpc0_cfg_qm_tensor_0_regs.h 04-Dec-2025 19:36 1870
dcore0_tpc0_cfg_regs.h 04-Dec-2025 19:36 5995
dcore0_tpc0_cfg_special_regs.h 04-Dec-2025 19:36 5228
dcore0_tpc0_eml_busmon_0_regs.h 04-Dec-2025 19:36 4177
dcore0_tpc0_eml_etf_regs.h 04-Dec-2025 19:36 2614
dcore0_tpc0_eml_funnel_regs.h 04-Dec-2025 19:36 1852
dcore0_tpc0_eml_spmu_regs.h 04-Dec-2025 19:36 3742
dcore0_tpc0_eml_stm_regs.h 04-Dec-2025 19:36 3160
dcore0_tpc0_qm_arc_aux_regs.h 04-Dec-2025 19:36 18455
dcore0_tpc0_qm_axuser_nonsecured_regs.h 04-Dec-2025 19:36 1839
dcore0_tpc0_qm_cgm_regs.h 04-Dec-2025 19:36 681
dcore0_tpc0_qm_regs.h 04-Dec-2025 19:36 28411
dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h 04-Dec-2025 19:36 1862
dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h 04-Dec-2025 19:36 2023
dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h 04-Dec-2025 19:36 1977
dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h 04-Dec-2025 19:36 1977
dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h 04-Dec-2025 19:36 1977
dcore0_vdec0_brdg_ctrl_masks.h 04-Dec-2025 19:36 28150
dcore0_vdec0_brdg_ctrl_regs.h 04-Dec-2025 19:36 7529
dcore0_vdec0_ctrl_special_regs.h 04-Dec-2025 19:36 5398
dcore1_mme_ctrl_lo_regs.h 04-Dec-2025 19:36 4447
dcore3_mme_ctrl_lo_regs.h 04-Dec-2025 19:36 4447
gaudi2_blocks_linux_driver.h 04-Dec-2025 19:36 2456864
gaudi2_regs.h 04-Dec-2025 19:36 25014
nic0_qm0_cgm_regs.h 04-Dec-2025 19:36 639
nic0_qm0_regs.h 04-Dec-2025 19:36 25285
nic0_qm_arc_aux0_regs.h 04-Dec-2025 19:36 16727
nic0_qpc0_regs.h 04-Dec-2025 19:36 22207
nic0_umr0_0_completion_queue_ci_1_regs.h 04-Dec-2025 19:36 757
nic0_umr0_0_unsecure_doorbell0_regs.h 04-Dec-2025 19:36 893
pcie_aux_regs.h 04-Dec-2025 19:36 6788
pcie_dbi_regs.h 04-Dec-2025 19:36 11034
pcie_dec0_cmd_masks.h 04-Dec-2025 19:36 9405
pcie_dec0_cmd_regs.h 04-Dec-2025 19:36 1850
pcie_vdec0_brdg_ctrl_axuser_dec_regs.h 04-Dec-2025 19:36 1816
pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h 04-Dec-2025 19:36 1977
pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h 04-Dec-2025 19:36 1931
pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h 04-Dec-2025 19:36 1931
pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h 04-Dec-2025 19:36 1931
pcie_vdec0_brdg_ctrl_masks.h 04-Dec-2025 19:36 27250
pcie_vdec0_brdg_ctrl_regs.h 04-Dec-2025 19:36 7299
pcie_vdec0_ctrl_special_regs.h 04-Dec-2025 19:36 5228
pcie_wrap_regs.h 04-Dec-2025 19:36 14625
pcie_wrap_special_regs.h 04-Dec-2025 19:36 4718
pdma0_core_ctx_axuser_regs.h 04-Dec-2025 19:36 1586
pdma0_core_ctx_regs.h 04-Dec-2025 19:36 2260
pdma0_core_masks.h 04-Dec-2025 19:36 15596
pdma0_core_regs.h 04-Dec-2025 19:36 3670
pdma0_core_special_masks.h 04-Dec-2025 19:36 5901
pdma0_qm_arc_aux_regs.h 04-Dec-2025 19:36 16727
pdma0_qm_axuser_nonsecured_regs.h 04-Dec-2025 19:36 1701
pdma0_qm_axuser_secured_regs.h 04-Dec-2025 19:36 1632
pdma0_qm_cgm_regs.h 04-Dec-2025 19:36 639
pdma0_qm_masks.h 04-Dec-2025 19:36 45224
pdma0_qm_regs.h 04-Dec-2025 19:36 25285
pdma1_core_ctx_axuser_regs.h 04-Dec-2025 19:36 1586
pdma1_qm_axuser_nonsecured_regs.h 04-Dec-2025 19:36 1701
pmmu_hbw_stlb_masks.h 04-Dec-2025 19:36 14948
pmmu_hbw_stlb_regs.h 04-Dec-2025 19:36 3759
pmmu_pif_regs.h 04-Dec-2025 19:36 3233
psoc_etr_masks.h 04-Dec-2025 19:36 10146
psoc_etr_regs.h 04-Dec-2025 19:36 2222
psoc_global_conf_masks.h 04-Dec-2025 19:36 65365
psoc_global_conf_regs.h 04-Dec-2025 19:36 35389
psoc_reset_conf_masks.h 04-Dec-2025 19:36 100195
psoc_reset_conf_regs.h 04-Dec-2025 19:36 27900
psoc_timestamp_regs.h 04-Dec-2025 19:36 1251
rot0_desc_regs.h 04-Dec-2025 19:36 3262
rot0_masks.h 04-Dec-2025 19:36 9894
rot0_qm_arc_aux_regs.h 04-Dec-2025 19:36 16439
rot0_qm_axuser_nonsecured_regs.h 04-Dec-2025 19:36 1678
rot0_qm_cgm_regs.h 04-Dec-2025 19:36 632
rot0_qm_regs.h 04-Dec-2025 19:36 24764
rot0_regs.h 04-Dec-2025 19:36 2180
xbar_edge_0_regs.h 04-Dec-2025 19:36 4834
xbar_mid_0_regs.h 04-Dec-2025 19:36 4742